Not Applicable.
Not Applicable.
1. Field of the Invention
The present invention relates to microelectronics and, in particular, to a method of fabricating an ultra-shallow junction in Field Effect Transistor (FET) devices, such as Bipolar and Complementary Metal Oxide Semiconductor (CMOS) devices. As used in this patent, an xe2x80x9cFETxe2x80x9d comprises a micro-electronic device having a source region and a drain region formed in mutually spaced adjacency in the surface of a semiconductor substrate, having a pair of the shallow implant regions being disposed between and formed as spaced-apart extensions of source and drain regions to form a channel region between the spaced-apart shallow implant regions, and a gate electrode overlying the channel region.
2. Description of Related Art
Advances in the miniaturization of CMOS devices have been a key driving force behind the explosive growth of various network centric computing products. Smaller CMOS devices typically equate to faster switching times that lead to faster and better performance.
The process of miniaturizing CMOS devices involves scaling down various horizontal and vertical dimensions of the CMOS device structure. In particular, the thickness of the ion implanted source/drain junction of a p-type or n-type transistor can be scaled down with a corresponding scaled increase in the substrate channel doping. Continued scaling of silicon device dimensions down to sub-100 nm dimensions requires highly doped ultra-shallow junctions.
The formation of source/drain extension junctions in CMOS devices is commonly carried out by the implantation of ions in appropriately masked source/drain regions of a silicon substrate with boron (p-type) or arsenic and phosphorous (n-type) dopants. However, ion implantation also creates extensive crystal damage and excess silicon interstitials. Silicon interstitials are displaced silicon atoms created by ion bombardment of the crystalline silicon substrate. In order to activate implanted dopants and remove implantation-induced damages, high temperature annealing at temperature, typically in the range between 800xc2x0 C. and 1200xc2x0 C., is needed. During thermal annealing, however, the presence of these excess silicon interstitials greatly enhances (10 to 1000 times the normal) diffusion of dopants through the silicon substrate, and results in a much deeper source/drain junction and a poorer junction profile.
In order to increase dopant concentration and minimize boron enhanced diffusion, advanced annealing techniques like spike annealing or impulse annealing currently are used. The strategy behind these annealing methods is to expose the samples at the peak temperature for little or no dwell time. A patent by Chuang entitled xe2x80x9cMethod to Improve Resistance Uniformity and Repeatability for Low Energy Ion Implantationxe2x80x9d, U.S. Pat. No. 6,362,081, discloses using a spike annealing process for recovering the crystalline structure of the damage silicon layer which results from the low energy ion implantation process. The full disclosure of U.S. Pat. No. 6,362,081 is incorporated into this patent. The rapid thermal annealing (RTA) is executed by rapidly heating the silicon layer to a specific temperature and then instantaneously lowering the specific temperature to a room temperature. The specific temperature is 1100xc2x0 C.
However, stability of those junctions formed by spike annealing is very poor. Dopant stabilization is important to device performance. If spike annealing cannot repair the implantation damage completely, or if new interstitial sources are generated during spike annealing, the interstitials will cause the dopants to redistribute, and deepen the junction depth during subsequent low temperature processes.
Instability is also an issue for junctions fabricated by alternative methods. A patent issued to D. J. Eaglesham and H.-J. Gossmann, entitled xe2x80x9cForming A Semiconductor Layer Using Molecular Beam Epitaxy,xe2x80x9d U.S. Pat. No. 5,169,798, discloses producing junctions by molecular beam epitaxy (MBE) growth. The full disclosure of U.S. Pat. No. 5,169,798 is incorporated into this patent. It has been shown that junctions formed by MBE are not stable during subsequent thermal processes. Such instability reduces the potential of MBE growth as an intergratable method for junction formation due to necessary high-temperature post-growth steps such as ohmic contact formation. For example, TiSi2, a predominant silicide used for interconnects to CMOS devices, requires a temperature higher than 700xc2x0 C. to form a low resisitivity, stable phase.
Other related art is disclosed in the following references, all of which are incorporated into this patent by this reference:
1. Lin Shao et al. xe2x80x9cStability of Ultra-Shallow Junction Formed by Low Energy Boron Implant and Spike Annealingxe2x80x9d. J. Appl. Phys. 92, 5788(2002).
2. P. E. Thompson and J. Bennet, xe2x80x9cFormation and Thermal Stability of Ultra-Shallow p+ Junctions in Si and Si1-xGex Formed By Molecular Beam Epitaxyxe2x80x9d, J. Appl. Phys. 92, 6845 (2002).
3. Aliette Mouroux, et al., xe2x80x9cPhase Formation and Resistivity In The Ternary System Tixe2x80x94Nbxe2x80x94Sixe2x80x9d, J. Appl. Phys. 86, 2323.
What is needed is a solution to overcome the instability of semiconductor junctions.
The present invention provides a method of forming a microelectronic structure on a semiconductor wafer having a silicon surface layer on a substrate comprising the following steps: implanting dopant ions into the surface layer; cleaning and oxidizing the surface layer, subjecting the structure to a first rapid thermal annealing process, including a first cooling process; subjecting the structure to a second thermal annealing process, including a second cooling process.
The first annealing process, accomplished via rapid annealing, comprises subjecting the structure to thermal annealing with temperature and time of the annealing, as well as the heating and cooling rates, selected such that a majority of dopants are electrically activated, and a majority of substrate damage is repaired. The second annealing process is performed with temperature, duration, and heating and cooling rates selected such that minimal dopant diffusion occurs.
The first annealing process uses a temperature range of 800xc2x0 C. to 1200xc2x0 C. for a duration from about a fraction of a second to less than about 1000 seconds, with a ramp-up rate of about 50xc2x0 C./second to about 1000xc2x0 C./second. The second annealing process uses a temperature range of 400xc2x0 C. to 650xc2x0 C. for a time period of from about 1 second to about 10 hours, and more preferably, from about 60 seconds to about 1 hour. An advantage of the present invention is that it can be used to make structures that are useful in fabrication of microelectronic devices, such as FET or CMOS devices, with significantly enhanced stability during followed thermal processes.